1. Technical Field
The present disclosure relates to the field of integrated circuit design. The present disclosure relates, more particularly, to metal interconnections within an integrated circuit die.
2. Description of the Related Art
As integrated circuit technology continues to scale down to smaller technology nodes, the back end of the line connections become very challenging and complicated to implement. Complex patterning schemes such as double patterning are used to provide smaller and smaller interconnection features. Many problems can occur within the integrated circuits as vias and metal tracks within the integrated circuit become smaller and closer together. These problems can include difficulty in alignment of photolithography masks during manufacture, as well as electromigration and time dependent dielectric breakdown during the life of the integrated circuit.
As feature sizes of integrated circuit dies shrink, it also becomes very difficult to maintain large distances between metal tracks of adjacent metal layers in order to keep the capacitance between metal tracks and adjacent metal layers low. As the capacitance between metal tracks increases, the signal propagation speed decreases. Thus, decreasing the capacitance has the effect of allowing for increased signal speeds. This typically entails maintaining large distances between the two metal layers. In order to do this, high aspect ratio vias are used. The making of high aspect ratio vias in technology nodes at or below 32 nm can become very problematic.